IVML > People > Phivos Mylonas
PDF) Accumulator-Based Weighted Pattern Generation.
PDF) Concurrent Self-Test with Partially Specified Patterns For Low Test Latency and Overhead
PDF) Delay-Insensitive Cell Matrix.
PDF) Detection of Delay Faults in Memory Address Decoders
PDF) On the Generation of Functional Test Programs for the Cache Replacement Logic
PDF) A Context-Aware Meeting Room: Mobile Interaction and Collaboration Using Android, Java ME and Windows Mobile
PDF) Moduli Set Selection and Cost Estimation for RNS-Based FIR Filter and Filter Bank Design
PDF) UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations
PDF) Symmetry Measure for Memory Test and Its Application in BIST Optimization
PDF) New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults
PDF) An adaptive BIST to detect multiple stuck-open faults in CMOS circuits
PDF) Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata
PDF) Survival analysis for modeling critical events that communities may undergo in dynamic social networks
PDF) A domain-specific approach for software development on Manycore platforms
ERCIM News 96 by Peter Kunz - Issuu
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) Modeling and Simulation of Efficient March Algorithm for Memory Testing
Latest Award Winners
PDF) Extending Internet into Space – ESA DTN Testbed Implementation and Evaluation
PDF) Multimode scan: Test per clock BIST for IP cores
Education and Information Technologies | Home
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique
PDF) High-Level Test Synthesis for Delay Fault Testability
NiDS2022 (Novel & Intelligent Digital Systems) - ATHENS
